Next: Flash Programming, Previous: CPU Configuration, Up: Top [Contents][Index]
OpenOCD has different commands for NOR and NAND flash; the “flash” command works with NOR flash, while the “nand” command works with NAND flash. This partially reflects different hardware technologies: NOR flash usually supports direct CPU instruction and data bus access, while data from a NAND flash must be copied to memory before it can be used. (SPI flash must also be copied to memory before use.) However, the documentation also uses “flash” as a generic term; for example, “Put flash configuration in board-specific files”.
Flash Steps:
flash bank
flash subcommand
Many CPUs have the ablity to “boot” from the first flash bank. This means that misprogramming that bank can “brick” a system, so that it can’t boot. JTAG tools, like OpenOCD, are often then used to “de-brick” the board by (re)installing working boot firmware.
Configures a flash bank which provides persistent storage for addresses from base to base + size - 1. These banks will often be visible to GDB through the target’s memory map. In some cases, configuring a flash bank will activate extra commands; see the driver-specific documentation.
cfi for external flash, or else
the name of a microcontroller with embedded flash memory.
See Flash Driver List.
Note: This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.
Prints a one-line summary of each device that was
declared using flash bank, numbered from zero.
Note that this is the plural form;
the singular form is a very different command.
Retrieves a list of associative arrays for each device that was
declared using flash bank, numbered from zero.
This returned list can be manipulated easily from within scripts.
Identify the flash, or validate the parameters of the configured flash. Operation
depends on the flash type.
The num parameter is a value shown by flash banks.
Most flash commands will implicitly autoprobe the bank;
flash drivers can distinguish between probing and autoprobing,
but most don’t bother.
One feature distinguishing NOR flash from NAND or serial flash technologies
is that for read access, it acts exactly like any other addressible memory.
This means you can use normal memory read commands like mdw or
dump_image with it, with no special flash subcommands.
See Memory access, and Image access.
Write access works differently. Flash memory normally needs to be erased before it’s written. Erasing a sector turns all of its bits to ones, and writing can turn ones into zeroes. This is why there are special commands for interactive erasing and writing, and why GDB needs to know which parts of the address space hold NOR flash memory.
Note: Most of these erase and write commands leverage the fact that NOR flash chips consume target address space. They implicitly refer to the current JTAG target, and map from an address in that target’s address space back to a flash bank. A few commands use abstract addressing based on bank and sector numbers, and don’t depend on searching the current target and its address space. Avoid confusing the two command models.
Some flash chips implement software protection against accidental writes, since such buggy writes could in some cases “brick” a system. For such systems, erasing and writing may require sector protection to be disabled first. Examples include CFI flash such as “Intel Advanced Bootblock flash”, and AT91SAM7 on-chip flash. See flash protect.
Erase sectors in bank num, starting at sector first
up to and including last.
Sector numbering starts at 0.
Providing a last sector of last
specifies "to the end of the flash bank".
The num parameter is a value shown by flash banks.
Erase sectors starting at address for length bytes. Unless pad is specified, address must begin a flash sector, and address + length - 1 must end a sector. Specifying pad erases extra data at the beginning and/or end of the specified region, as needed to erase only full sectors. The flash bank to use is inferred from the address, and the specified length must stay within that bank. As a special case, when length is zero and address is the start of the bank, the whole flash is erased. If unlock is specified, then the flash is unprotected before erase starts.
Fills flash memory with the specified word (32 bits), halfword (16 bits), or byte (8-bit) pattern, starting at address and continuing for length units (word/halfword/byte). No erasure is done before writing; when needed, that must be done before issuing this command. Writes are done in blocks of up to 1024 bytes, and each write is verified by reading back the data and comparing it to what was written. The flash bank to use is inferred from the address of each block, and the specified length must stay within that bank.
Write the binary filename to flash bank num,
starting at offset bytes from the beginning of the bank.
The num parameter is a value shown by flash banks.
Write the image filename to the current target’s flash bank(s). A relocation offset may be specified, in which case it is added to the base address for each section in the image. The file [type] can be specified explicitly as bin (binary), ihex (Intel hex), elf (ELF file), s19 (Motorola s19). mem, or builder. The relevant flash sectors will be erased prior to programming if the erase parameter is given. If unlock is provided, then the flash banks are unlocked before erase and program. The flash bank to use is inferred from the address of each image section.
Warning: Be careful using the erase flag when the flash is holding data you want to preserve. Portions of the flash outside those described in the image’s sections might be erased with no notice.
- When a section of the image being written does not fill out all the sectors it uses, the unwritten parts of those sectors are necessarily also erased, because sectors can’t be partially erased.
- Data stored in sector "holes" between image sections are also affected. For example, "
flash write_image erase ..." of an image with one byte at the beginning of a flash bank and one byte at the end erases the entire bank – not just the two sectors being written.Also, when flash protection is important, you must re-apply it after it has been removed by the unlock flag.
Check erase state of sectors in flash bank num,
and display that status.
The num parameter is a value shown by flash banks.
Print info about flash bank num
The num parameter is a value shown by flash banks.
This command will first query the hardware, it does not print cached
and possibly stale information.
Enable (on) or disable (off) protection of flash sectors
in flash bank num, starting at sector first
and continuing up to and including last.
Providing a last sector of last
specifies "to the end of the flash bank".
The num parameter is a value shown by flash banks.
Sets the default value used for padding any image sections, This should normally match the flash bank erased value. If not specified by this comamnd or the flash driver then it defaults to 0xff.
This is a helper script that simplifies using OpenOCD as a standalone programmer. The only required parameter is filename, the others are optional. See Flash Programming.
As noted above, the flash bank command requires a driver name,
and allows driver-specific options and behaviors.
Some drivers also activate driver-specific commands.
The “Common Flash Interface” (CFI) is the main standard for
external NOR flash chips, each of which connects to a
specific external chip select on the CPU.
Frequently the first such chip is used to boot the system.
Your board’s reset-init handler might need to
configure additional chip selects using other commands (like: mww to
configure a bus and its timings), or
perhaps configure a GPIO pin that controls the “write protect” pin
on the flash chip.
The CFI driver can use a target-specific working area to significantly
speed up operation.
The CFI driver can accept the following optional parameters, in any order:
To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes) wide on a sixteen bit bus:
flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
To configure one bank of 32 MBytes built from two sixteen bit (two byte) wide parts wired in parallel to create a thirty-two bit (four byte) bus with doubled throughput:
flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
NXP’s LPC43xx and LPC18xx families include a proprietary SPI Flash Interface (SPIFI) peripheral that can drive and provide memory mapped access to external SPI flash devices.
The lpcspifi driver initializes this interface and provides program and erase functionality for these serial flash devices. Use of this driver requires a working area of at least 1kB to be configured on the target device; more than this will significantly reduce flash programming times.
The setup command only requires the base parameter. All other parameters are ignored, and the flash size and layout are configured by the driver.
flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
Some devices form STMicroelectronics (e.g. STR75x MCU family, SPEAr MPU family) include a proprietary “Serial Memory Interface” (SMI) controller able to drive external SPI flash devices. Depending on specific device and board configuration, up to 4 external flash devices can be connected.
SMI makes the flash content directly accessible in the CPU address
space; each external device is mapped in a memory bank.
CPU can directly read data, execute code and boot from SMI banks.
Normal OpenOCD commands like mdw can be used to display
the flash content.
The setup command only requires the base parameter in order to identify the memory bank. All other parameters are ignored. Additional information, like flash size, are detected automatically.
flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
The ADUC702x analog microcontrollers from Analog Devices include internal flash and use ARM7TDMI cores. The aduc702x flash driver works with models ADUC7019 through ADUC7028. The setup command only requires the target argument since all devices in this family have the same memory layout.
flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
All members of the AT91SAM3 microcontroller family from Atmel include internal flash and use ARM’s Cortex-M3 core. The driver currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note that the driver was orginaly developed and tested using the AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in the family was cribbed from the data sheet. Note to future readers/updaters: Please remove this worrysome comment after other chips are confirmed.
The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips have one flash bank. In all cases the flash banks are at the following fixed locations:
# Flash bank 0 - all chips flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME # Flash bank 1 - only 256K chips flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
Internally, the AT91SAM3 flash memory is organized as follows.
Unlike the AT91SAM7 chips, these are not used as parameters
to the flash bank command:
The AT91SAM3 driver adds some additional commands:
With no parameters, show or show all,
shows the status of all GPNVM bits.
With show number, displays that bit.
With set number or clear number,
modifies that GPNVM bit.
This command attempts to display information about the AT91SAM3
chip. First it read the CHIPID_CIDR [address 0x400e0740, see
Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
document id: doc6430A] and decodes the values. Second it reads the
various clock configuration registers and attempts to display how it
believes the chip is configured. By default, the SLOWCLK is assumed to
be 32768 Hz, see the command at91sam3 slowclk.
This command shows/sets the slow clock frequency used in the
at91sam3 info command calculations above.
All members of the AT91SAM4 microcontroller family from Atmel include internal flash and use ARM’s Cortex-M4 core. This driver uses the same cmd names/syntax as See at91sam3.
All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
For chips which are not recognized by the controller driver, you must provide additional parameters in the following order:
flash info
It is recommended that you provide zeroes for all of those values except the clock frequency, so that everything except that frequency will be autoconfigured. Knowing the frequency helps ensure correct timings for flash access.
The flash controller handles erases automatically on a page (128/256 byte)
basis, so explicit erase commands are not necessary for flash programming.
However, there is an “EraseAll“ command that can erase an entire flash
plane (of up to 256KB), and it will be used automatically when you issue
flash erase_sector or flash erase_address commands.
Set or clear a “General Purpose Non-Volatile Memory” (GPNVM) bit for the processor. Each processor has a number of such bits, used for controlling features such as brownout detection (so they are not truly general purpose).
Note: This assumes that the first flash bank (number 0) is associated with the appropriate at91sam7 target.
The AVR 8-bit microcontrollers from Atmel integrate flash memory. The current implementation is incomplete.
All members of the EFM32 microcontroller family from Energy Micro include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
The current implementation is incomplete. Unprotecting flash pages is not supported.
Most members of the LPC1700, LPC1800, LPC2000 and LPC4300 microcontroller families from NXP include internal flash and use Cortex-M3 (LPC1700, LPC1800), Cortex-M4 (LPC4300) or ARM7TDMI (LPC2000) cores.
Note: There are LPC2000 devices which are not supported by the lpc2000 driver: The LPC2888 is supported by the lpc288x driver. The LPC29xx family is supported by the lpc2900 driver.
The lpc2000 driver defines two mandatory and one optional parameters, which must appear in the following order:
Note: If you don’t provide calc_checksum when you’re writing the vector table, the boot ROM will almost certainly ignore your flash image. However, if you do provide it, with most tool chains
verify_imagewill fail.
LPC flashes don’t require the chip and bus width to be specified.
flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
lpc2000_v2 14765 calc_checksum
Displays the four byte part identifier associated with the specified flash bank.
The LPC2888 microcontroller from NXP needs slightly different flash support from its lpc2000 siblings. The lpc288x driver defines one mandatory parameter, the programming clock rate in Hz. LPC flashes don’t require the chip and bus width to be specified.
flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
This driver supports the LPC29xx ARM968E based microcontroller family from NXP.
The predefined parameters base, size, chip_width and
bus_width of the flash bank command are ignored. Flash size and
sector layout are auto-configured by the driver.
The driver has one additional mandatory parameter: The CPU clock rate
(in kHz) at the time the flash operations will take place. Most of the time this
will not be the crystal frequency, but a higher PLL frequency. The
reset-init event handler in the board script is usually the place where
you start the PLL.
The driver rejects flashless devices (currently the LPC2930).
The EEPROM in LPC2900 devices is not mapped directly into the address space.
It must be handled much more like NAND flash memory, and will therefore be
handled by a separate lpc2900_eeprom driver (not yet available).
Sector protection in terms of the LPC2900 is handled transparently. Every time a
sector needs to be erased or programmed, it is automatically unprotected.
What is shown as protection status in the flash info command, is
actually the LPC2900 sector security. This is a mechanism to prevent a
sector from ever being erased or programmed again. As this is an irreversible
mechanism, it is handled by a special command (lpc2900 secure_sector),
and not by the standard flash protect command.
Example for a 125 MHz clock frequency:
flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
Some lpc2900-specific commands are defined. In the following command list,
the bank parameter is the bank number as obtained by the
flash banks command.
Calculates a 128-bit hash value, the signature, from the whole flash content. This is a hardware feature of the flash block, hence the calculation is very fast. You may use this to verify the content of a programmed device against a known signature. Example:
lpc2900 signature 0 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
Reads the 912 bytes of customer information from the flash index sector, and saves it to a file in binary format. Example:
lpc2900 read_custom 0 /path_to/customer_info.bin
The index sector of the flash is a write-only sector. It cannot be
erased! In order to guard against unintentional write access, all following
commands need to be preceeded by a successful call to the password
command:
You need to use this command right before each of the following commands:
lpc2900 write_custom, lpc2900 secure_sector,
lpc2900 secure_jtag.
The password string is fixed to "I_know_what_I_am_doing". Example:
lpc2900 password 0 I_know_what_I_am_doing Potentially dangerous operation allowed in next command!
Writes the content of the file into the customer info space of the flash index sector. The filetype can be specified with the type field. Possible values for type are: bin (binary), ihex (Intel hex format), elf (ELF binary) or s19 (Motorola S-records). The file must contain a single section, and the contained data length must be exactly 912 bytes.
Attention: This cannot be reverted! Be careful!
Example:
lpc2900 write_custom 0 /path_to/customer_info.bin bin
Secures the sector range from first to last (including) against further program and erase operations. The sector security will be effective after the next power cycle.
Attention: This cannot be reverted! Be careful!
Secured sectors appear as protected in the flash info command.
Example:
lpc2900 secure_sector 0 1 1
flash info 0
#0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
# 0: 0x00000000 (0x2000 8kB) not protected
# 1: 0x00002000 (0x2000 8kB) protected
# 2: 0x00004000 (0x2000 8kB) not protected
Irreversibly disable the JTAG port. The new JTAG security setting will be effective after the next power cycle.
Attention: This cannot be reverted! Be careful!
Examples:
lpc2900 secure_jtag 0
No idea what this is, other than using some arm7/arm9 core.
flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
The PIC32MX microcontrollers are based on the MIPS 4K cores, and integrate flash memory.
flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
Some pic32mx-specific commands are defined:
Programs the specified 32-bit value at the given address in the specified chip bank.
Unlock and erase specified chip bank. This will remove any Code Protection.
All members of the Stellaris LM3Sxxx microcontroller family from Texas Instruments include internal flash and use ARM Cortex M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. 6
flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
Performs the Recovering a "Locked" Device procedure to restore the flash specified by bank_id and its associated nonvolatile registers to their factory default values (erased). This is the only way to remove flash protection or re-enable debugging if that capability has been disabled.
Note that the final "power cycle the chip" step in this procedure must be performed by hand, since OpenOCD can’t do it.
Warning: if more than one Stellaris chip is connected, the procedure is applied to all of them.
All members of the STM32F0, STM32F1 and STM32F3 microcontroller families from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
If you have a target with dual flash banks then define the second bank as per the following example.
flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
Some stm32f1x-specific commands 7 are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Read and display the stm32 option bytes written by
the stm32f1x options_write command.
The num parameter is a value shown by flash banks.
Writes the stm32 option byte with the specified values.
The num parameter is a value shown by flash banks.
All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics include internal flash and use ARM Cortex-M3/M4 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
Some stm32f2x-specific commands are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
All members of the STM32L microcontroller families from ST Microelectronics include internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32lx 0 0x20000 0 0 $_TARGETNAME
All members of the STR7 microcontroller family from ST Microelectronics
include internal flash and use ARM7TDMI cores.
The str7x driver defines one mandatory parameter, variant,
which is either STR71x, STR73x or STR75x.
flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
Activate the Debug/Readout protection mechanism for the specified flash bank.
Most members of the STR9 microcontroller family from ST Microelectronics
include internal flash and use ARM966E cores.
The str9 needs the flash controller to be configured using
the str9x flash_config command prior to Flash programming.
flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME str9x flash_config 0 4 2 0 0x80000
Configures the str9 flash controller.
The num parameter is a value shown by flash banks.
Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. This driver doesn’t require the chip and bus width to be specified.
Some tms470-specific commands are defined:
Saves programming keys in a register, to enable flash erase and write commands.
Reports the clock speed, which is used to calculate timings.
Disables (1) or enables (0) use of the PLL to speed up the flash clock.
This is a special driver that maps a previously defined bank to another address. All bank settings will be copied from the master physical bank.
The virtual driver defines one mandatory parameters,
So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to the flash bank defined at address 0x1fc00000. Any cmds executed on the virtual banks are actually performed on the physical banks.
flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
All members of the FM3 microcontroller family from Fujitsu
include internal flash and use ARM Cortex M3 cores.
The fm3 driver uses the target parameter to select the
correct bank config, it can currently be one of the following:
mb9bfxx1.cpu, mb9bfxx2.cpu, mb9bfxx3.cpu,
mb9bfxx4.cpu, mb9bfxx5.cpu or mb9bfxx6.cpu.
flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
Here is some background info to help you better understand how this driver works. OpenOCD has two flash drivers for the str9:
Before we run any commands using the str9xpec driver we must first disable the str9 core. This example assumes the str9xpec driver has been configured for flash bank 0.
# assert srst, we do not want core running # while accessing str9xpec flash driver jtag_reset 0 1 # turn off target polling poll off # disable str9 core str9xpec enable_turbo 0 # read option bytes str9xpec options_read 0 # re-enable str9 core str9xpec disable_turbo 0 poll on reset halt
The above example will read the str9 option bytes. When performing a unlock remember that you will not be able to halt the str9 - it has been locked. Halting the core is not required for the str9xpec driver as mentioned above, just issue the commands above manually or from a telnet prompt.
Only use this driver for locking/unlocking the device or configuring the option bytes.
Use the standard str9 driver for programming.
Before using the flash commands the turbo mode must be enabled using the
str9xpec enable_turbo command.
Several str9xpec-specific commands are defined:
Restore the str9 into JTAG chain.
Enable turbo mode, will simply remove the str9 from the chain and talk directly to the embedded flash controller.
Lock str9 device. The str9 will only respond to an unlock command that will erase the device.
Prints the part identifier for bank num.
Configure str9 boot bank.
Configure str9 lvd source.
Configure str9 lvd threshold.
Configure str9 lvd reset warning source.
Read str9 option bytes.
Write str9 option bytes.
unlock str9 device.
All members of the nRF51 microcontroller families from Nordic Semiconductor include internal flash and use ARM Cortex-M0 core.
flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
Some nrf51-specific commands are defined:
Erases the contents of the code memory and user information configuration registers as well. It must be noted that this command works only for chips that do not have factory pre-programmed region 0 code.
Configures a mflash for soc host bank at address base. The pin number format depends on the host GPIO naming convention. Currently, the mflash driver supports s3c2440 and pxa270.
Example for s3c2440 mflash where RST pin is GPIO B1:
mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
Example for pxa270 mflash where RST pin is GPIO 43:
mflash bank $_FLASHNAME pxa270 0x08000000 43 0
Configure mflash PLL. The frequency is the mflash input frequency, in Hz. Issuing this command will erase mflash’s whole internal nand and write new pll. After this command, mflash needs power-on-reset for normal operation. If pll was newly configured, storage and boot(optional) info also need to be update.
Configure bootable option. If bootable option is set, mflash offer the first 8 sectors (4kB) for boot.
Configure storage information. For the normal storage operation, this information must be written.
Dump size bytes, starting at offset bytes from the beginning of the bank num, to the file named filename.
Probe mflash.
Write the binary file filename to mflash bank num, starting at offset bytes from the beginning of the bank.
Currently there is a stellaris mass_erase command.
That seems pointless since the same effect can be had using the
standard flash erase_address command.
Currently there is a stm32f1x mass_erase command.
That seems pointless since the same effect can be had using the
standard flash erase_address command.
Next: Flash Programming, Previous: CPU Configuration, Up: Top [Contents][Index]