Class GenBuffer::Sub
   size=32 align=8
   base size=32 base align=8
GenBuffer::Sub (0x0x7f155748bc60) 0

Class GenBuffer::SubW
   size=32 align=8
   base size=32 base align=8
GenBuffer::SubW (0x0x7f155748bcc0) 0

Vtable for GenBuffer::Writable
GenBuffer::Writable::_ZTVN9GenBuffer8WritableE: 8u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    (int (*)(...))__cxa_pure_virtual
24    (int (*)(...))__cxa_pure_virtual
32    0u
40    0u
48    (int (*)(...))GenBuffer::Writable::vformat
56    (int (*)(...))GenBuffer::Writable::vformat

Class GenBuffer::Writable
   size=8 align=8
   base size=8 base align=8
GenBuffer::Writable (0x0x7f155748bd20) 0 nearly-empty
    vptr=((& GenBuffer::Writable::_ZTVN9GenBuffer8WritableE) + 16u)

Vtable for GenBuffer::Readable
GenBuffer::Readable::_ZTVN9GenBuffer8ReadableE: 8u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    (int (*)(...))__cxa_pure_virtual
24    (int (*)(...))GenBuffer::Readable::vi_read
32    (int (*)(...))GenBuffer::Readable::vi_availh
40    (int (*)(...))GenBuffer::Readable::vi_rewind
48    0u
56    0u

Class GenBuffer::Readable
   size=8 align=8
   base size=8 base align=8
GenBuffer::Readable (0x0x7f155748bd80) 0 nearly-empty
    vptr=((& GenBuffer::Readable::_ZTVN9GenBuffer8ReadableE) + 16u)

Vtable for GenBuffer
GenBuffer::_ZTV9GenBuffer: 13u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    0u
24    0u
32    (int (*)(...))__cxa_pure_virtual
40    (int (*)(...))__cxa_pure_virtual
48    (int (*)(...))__cxa_pure_virtual
56    (int (*)(...))__cxa_pure_virtual
64    (int (*)(...))GenBuffer::operator void*
72    (int (*)(...))GenBuffer::operator!
80    (int (*)(...))GenBuffer::copyRange
88    (int (*)(...))GenBuffer::cmp
96    (int (*)(...))GenBuffer::cmp

Class GenBuffer
   size=8 align=8
   base size=8 base align=8
GenBuffer (0x0x7f155748bc00) 0 nearly-empty
    vptr=((& GenBuffer::_ZTV9GenBuffer) + 16u)

Vtable for SimBuffer::Flat
SimBuffer::Flat::_ZTVN9SimBuffer4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   (int (*)(...))SimBuffer::Flat::~Flat
112   (int (*)(...))SimBuffer::Flat::~Flat
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::Flat
SimBuffer::Flat::_ZTTN9SimBuffer4FlatE: 2u entries
0     ((& SimBuffer::Flat::_ZTVN9SimBuffer4FlatE) + 104u)
8     ((& SimBuffer::Flat::_ZTVN9SimBuffer4FlatE) + 104u)

Class SimBuffer::Flat
   size=24 align=8
   base size=24 base align=8
SimBuffer::Flat (0x0x7f15574b9d00) 0
    vptridx=0u vptr=((& SimBuffer::Flat::_ZTVN9SimBuffer4FlatE) + 104u)
  GenBuffer (0x0x7f155748be40) 0 nearly-empty virtual
      primary-for SimBuffer::Flat (0x0x7f15574b9d00)
      vptridx=8u vbaseoffset=-104

Vtable for SimBuffer::Static
SimBuffer::Static::_ZTVN9SimBuffer6StaticE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   (int (*)(...))SimBuffer::Static::~Static
112   (int (*)(...))SimBuffer::Static::~Static
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

Construction vtable for SimBuffer::Flat (0x0x7f15574b9dd0 instance) in SimBuffer::Static
SimBuffer::Static::_ZTCN9SimBuffer6StaticE0_NS_4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   0u
112   0u
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::Static
SimBuffer::Static::_ZTTN9SimBuffer6StaticE: 4u entries
0     ((& SimBuffer::Static::_ZTVN9SimBuffer6StaticE) + 104u)
8     ((& SimBuffer::Static::_ZTCN9SimBuffer6StaticE0_NS_4FlatE) + 104u)
16    ((& SimBuffer::Static::_ZTCN9SimBuffer6StaticE0_NS_4FlatE) + 104u)
24    ((& SimBuffer::Static::_ZTVN9SimBuffer6StaticE) + 104u)

Class SimBuffer::Static
   size=24 align=8
   base size=24 base align=8
SimBuffer::Static (0x0x7f15574b9d68) 0
    vptridx=0u vptr=((& SimBuffer::Static::_ZTVN9SimBuffer6StaticE) + 104u)
  SimBuffer::Flat (0x0x7f15574b9dd0) 0
      primary-for SimBuffer::Static (0x0x7f15574b9d68)
      subvttidx=8u
    GenBuffer (0x0x7f155748bea0) 0 nearly-empty virtual
        primary-for SimBuffer::Flat (0x0x7f15574b9dd0)
        vptridx=24u vbaseoffset=-104

Vtable for SimBuffer::Fixed
SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   (int (*)(...))SimBuffer::Fixed::~Fixed
112   (int (*)(...))SimBuffer::Fixed::~Fixed
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

Construction vtable for SimBuffer::Flat (0x0x7f15574b9ea0 instance) in SimBuffer::Fixed
SimBuffer::Fixed::_ZTCN9SimBuffer5FixedE0_NS_4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   0u
112   0u
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::Fixed
SimBuffer::Fixed::_ZTTN9SimBuffer5FixedE: 4u entries
0     ((& SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE) + 104u)
8     ((& SimBuffer::Fixed::_ZTCN9SimBuffer5FixedE0_NS_4FlatE) + 104u)
16    ((& SimBuffer::Fixed::_ZTCN9SimBuffer5FixedE0_NS_4FlatE) + 104u)
24    ((& SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE) + 104u)

Class SimBuffer::Fixed
   size=24 align=8
   base size=24 base align=8
SimBuffer::Fixed (0x0x7f15574b9e38) 0
    vptridx=0u vptr=((& SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE) + 104u)
  SimBuffer::Flat (0x0x7f15574b9ea0) 0
      primary-for SimBuffer::Fixed (0x0x7f15574b9e38)
      subvttidx=8u
    GenBuffer (0x0x7f155748bf00) 0 nearly-empty virtual
        primary-for SimBuffer::Flat (0x0x7f15574b9ea0)
        vptridx=24u vbaseoffset=-104

Vtable for SimBuffer::Appendable
SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE: 34u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551608u
168   (int (*)(...))-8
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

VTT for SimBuffer::Appendable
SimBuffer::Appendable::_ZTTN9SimBuffer10AppendableE: 2u entries
0     ((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 24u)
8     ((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 184u)

Class SimBuffer::Appendable
   size=16 align=8
   base size=8 base align=8
SimBuffer::Appendable (0x0x7f1557543150) 0 nearly-empty
    vptridx=0u vptr=((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 24u)
  GenBuffer (0x0x7f155748bf60) 8 nearly-empty virtual
      vptridx=8u vbaseoffset=-24 vptr=((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 184u)
  GenBuffer::Writable (0x0x7f155754c000) 0 nearly-empty
      primary-for SimBuffer::Appendable (0x0x7f1557543150)

Class SimBuffer::Linked::Node
   size=24 align=8
   base size=24 base align=8
SimBuffer::Linked::Node (0x0x7f155754c120) 0

Vtable for SimBuffer::Linked
SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE: 38u entries
0     24u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    (int (*)(...))SimBuffer::Linked::~Linked
48    (int (*)(...))SimBuffer::Linked::~Linked
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))SimBuffer::Linked::vi_mkend
80    (int (*)(...))SimBuffer::Linked::vi_mkbeg
88    (int (*)(...))SimBuffer::Linked::getLength
96    (int (*)(...))SimBuffer::Linked::each_sub
104   (int (*)(...))SimBuffer::Linked::first_sub
112   (int (*)(...))SimBuffer::Linked::next_sub
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551592u
168   18446744073709551592u
176   18446744073709551592u
184   18446744073709551592u
192   18446744073709551592u
200   (int (*)(...))-24
208   (int (*)(...))0
216   (int (*)(...))SimBuffer::Linked::_ZTv0_n24_N9SimBuffer6LinkedD1Ev
224   (int (*)(...))SimBuffer::Linked::_ZTv0_n24_N9SimBuffer6LinkedD0Ev
232   (int (*)(...))SimBuffer::Linked::_ZTv0_n32_NK9SimBuffer6Linked9getLengthEv
240   (int (*)(...))SimBuffer::Linked::_ZTv0_n40_NK9SimBuffer6Linked8each_subEPFvPKcmPvES3_
248   (int (*)(...))SimBuffer::Linked::_ZTv0_n48_NK9SimBuffer6Linked9first_subERN9GenBuffer3SubE
256   (int (*)(...))SimBuffer::Linked::_ZTv0_n56_NK9SimBuffer6Linked8next_subERN9GenBuffer3SubE
264   (int (*)(...))GenBuffer::operator void*
272   (int (*)(...))GenBuffer::operator!
280   (int (*)(...))GenBuffer::copyRange
288   (int (*)(...))GenBuffer::cmp
296   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Appendable (0x0x7f15575432a0 instance) in SimBuffer::Linked
SimBuffer::Linked::_ZTCN9SimBuffer6LinkedE0_NS_10AppendableE: 34u entries
0     24u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551592u
168   (int (*)(...))-24
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

VTT for SimBuffer::Linked
SimBuffer::Linked::_ZTTN9SimBuffer6LinkedE: 4u entries
0     ((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 24u)
8     ((& SimBuffer::Linked::_ZTCN9SimBuffer6LinkedE0_NS_10AppendableE) + 24u)
16    ((& SimBuffer::Linked::_ZTCN9SimBuffer6LinkedE0_NS_10AppendableE) + 184u)
24    ((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 216u)

Class SimBuffer::Linked
   size=32 align=8
   base size=24 base align=8
SimBuffer::Linked (0x0x7f15574b9f70) 0
    vptridx=0u vptr=((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 24u)
  SimBuffer::Appendable (0x0x7f15575432a0) 0 nearly-empty
      primary-for SimBuffer::Linked (0x0x7f15574b9f70)
      subvttidx=8u
    GenBuffer (0x0x7f155754c060) 24 nearly-empty virtual
        vptridx=24u vbaseoffset=-24 vptr=((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 216u)
    GenBuffer::Writable (0x0x7f155754c0c0) 0 nearly-empty
        primary-for SimBuffer::Appendable (0x0x7f15575432a0)

Vtable for SimBuffer::Resizable
SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE: 35u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))SimBuffer::Resizable::vi_mkend
80    (int (*)(...))SimBuffer::Resizable::vi_mkbeg
88    (int (*)(...))__cxa_pure_virtual
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   0u
168   18446744073709551608u
176   (int (*)(...))-8
184   (int (*)(...))0
192   0u
200   0u
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))__cxa_pure_virtual
240   (int (*)(...))GenBuffer::operator void*
248   (int (*)(...))GenBuffer::operator!
256   (int (*)(...))GenBuffer::copyRange
264   (int (*)(...))GenBuffer::cmp
272   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Appendable (0x0x7f1557543620 instance) in SimBuffer::Resizable
SimBuffer::Resizable::_ZTCN9SimBuffer9ResizableE0_NS_10AppendableE: 34u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551608u
168   (int (*)(...))-8
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

VTT for SimBuffer::Resizable
SimBuffer::Resizable::_ZTTN9SimBuffer9ResizableE: 4u entries
0     ((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 24u)
8     ((& SimBuffer::Resizable::_ZTCN9SimBuffer9ResizableE0_NS_10AppendableE) + 24u)
16    ((& SimBuffer::Resizable::_ZTCN9SimBuffer9ResizableE0_NS_10AppendableE) + 184u)
24    ((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 192u)

Class SimBuffer::Resizable
   size=16 align=8
   base size=8 base align=8
SimBuffer::Resizable (0x0x7f15574b9c98) 0 nearly-empty
    vptridx=0u vptr=((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 24u)
  SimBuffer::Appendable (0x0x7f1557543620) 0 nearly-empty
      primary-for SimBuffer::Resizable (0x0x7f15574b9c98)
      subvttidx=8u
    GenBuffer (0x0x7f155754c240) 8 nearly-empty virtual
        vptridx=24u vbaseoffset=-24 vptr=((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 192u)
    GenBuffer::Writable (0x0x7f155754c2a0) 0 nearly-empty
        primary-for SimBuffer::Appendable (0x0x7f1557543620)

Vtable for SimBuffer::B
SimBuffer::B::_ZTVN9SimBuffer1BE: 40u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::B::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    (int (*)(...))SimBuffer::B::~B
48    (int (*)(...))SimBuffer::B::~B
56    (int (*)(...))SimBuffer::B::vformat
64    (int (*)(...))SimBuffer::B::vformat
72    (int (*)(...))SimBuffer::Resizable::vi_mkend
80    (int (*)(...))SimBuffer::Resizable::vi_mkbeg
88    (int (*)(...))SimBuffer::B::vi_grow2
96    (int (*)(...))SimBuffer::B::operator void*
104   (int (*)(...))SimBuffer::B::operator!
112   0u
120   0u
128   0u
136   0u
144   18446744073709551608u
152   18446744073709551608u
160   0u
168   0u
176   0u
184   0u
192   18446744073709551608u
200   (int (*)(...))-8
208   (int (*)(...))0
216   (int (*)(...))SimBuffer::B::_ZThn8_N9SimBuffer1BD1Ev
224   (int (*)(...))SimBuffer::B::_ZThn8_N9SimBuffer1BD0Ev
232   (int (*)(...))SimBuffer::Flat::getLength
240   (int (*)(...))SimBuffer::Flat::each_sub
248   (int (*)(...))SimBuffer::Flat::first_sub
256   (int (*)(...))SimBuffer::Flat::next_sub
264   (int (*)(...))SimBuffer::B::_ZThn8_NK9SimBuffer1BcvPvEv
272   (int (*)(...))SimBuffer::B::_ZThn8_NK9SimBuffer1BntEv
280   (int (*)(...))SimBuffer::Flat::copyRange
288   (int (*)(...))GenBuffer::cmp
296   (int (*)(...))SimBuffer::Flat::cmp
304   (int (*)(...))SimBuffer::Flat::cmp
312   (int (*)(...))SimBuffer::Flat::getAt0

Construction vtable for SimBuffer::Resizable (0x0x7f15574b9f08 instance) in SimBuffer::B
SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_9ResizableE: 35u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))SimBuffer::Resizable::vi_mkend
80    (int (*)(...))SimBuffer::Resizable::vi_mkbeg
88    (int (*)(...))__cxa_pure_virtual
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   0u
168   18446744073709551608u
176   (int (*)(...))-8
184   (int (*)(...))0
192   0u
200   0u
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))__cxa_pure_virtual
240   (int (*)(...))GenBuffer::operator void*
248   (int (*)(...))GenBuffer::operator!
256   (int (*)(...))GenBuffer::copyRange
264   (int (*)(...))GenBuffer::cmp
272   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Appendable (0x0x7f15575437e0 instance) in SimBuffer::B
SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_10AppendableE: 34u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551608u
168   (int (*)(...))-8
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Flat (0x0x7f155738a000 instance) in SimBuffer::B
SimBuffer::B::_ZTCN9SimBuffer1BE8_NS_4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   0u
112   0u
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::B
SimBuffer::B::_ZTTN9SimBuffer1BE: 9u entries
0     ((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 24u)
8     ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_9ResizableE) + 24u)
16    ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_10AppendableE) + 24u)
24    ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_10AppendableE) + 184u)
32    ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_9ResizableE) + 192u)
40    ((& SimBuffer::B::_ZTCN9SimBuffer1BE8_NS_4FlatE) + 104u)
48    ((& SimBuffer::B::_ZTCN9SimBuffer1BE8_NS_4FlatE) + 104u)
56    ((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 216u)
64    ((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 216u)

Class SimBuffer::B
   size=48 align=8
   base size=48 base align=8
SimBuffer::B (0x0x7f1557543770) 0
    vptridx=0u vptr=((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 24u)
  SimBuffer::Resizable (0x0x7f15574b9f08) 0 nearly-empty
      primary-for SimBuffer::B (0x0x7f1557543770)
      subvttidx=8u
    SimBuffer::Appendable (0x0x7f15575437e0) 0 nearly-empty
        primary-for SimBuffer::Resizable (0x0x7f15574b9f08)
        subvttidx=16u
      GenBuffer (0x0x7f155754c300) 8 nearly-empty virtual
          primary-for SimBuffer::Flat (0x0x7f155738a000)
          vptridx=56u vbaseoffset=-24
      GenBuffer::Writable (0x0x7f155754c360) 0 nearly-empty
          primary-for SimBuffer::Appendable (0x0x7f15575437e0)
  SimBuffer::Flat (0x0x7f155738a000) 8
      subvttidx=40u vptridx=64u vptr=((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 216u)
    GenBuffer (0x0x7f155754c300) alternative-path

Class SimBuffer
   size=1 align=1
   base size=0 base align=1
SimBuffer (0x0x7f155748bde0) 0 empty

Vtable for Mapping::Gen
Mapping::Gen::_ZTVN7Mapping3GenE: 9u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    0u
24    0u
32    (int (*)(...))__cxa_pure_virtual
40    (int (*)(...))__cxa_pure_virtual
48    (int (*)(...))__cxa_pure_virtual
56    (int (*)(...))__cxa_pure_virtual
64    (int (*)(...))__cxa_pure_virtual

Class Mapping::Gen
   size=32 align=8
   base size=32 base align=8
Mapping::Gen (0x0x7f155754c420) 0
    vptr=((& Mapping::Gen::_ZTVN7Mapping3GenE) + 16u)

Class Mapping::DoubleHash::Ary
   size=16 align=8
   base size=16 base align=8
Mapping::DoubleHash::Ary (0x0x7f155754c4e0) 0

Vtable for Mapping::DoubleHash
Mapping::DoubleHash::_ZTVN7Mapping10DoubleHashE: 13u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    0u
24    0u
32    (int (*)(...))Mapping::DoubleHash::set
40    (int (*)(...))Mapping::DoubleHash::get
48    (int (*)(...))Mapping::DoubleHash::deletee
56    (int (*)(...))Mapping::DoubleHash::getFirst
64    (int (*)(...))Mapping::DoubleHash::getNext
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    (int (*)(...))__cxa_pure_virtual
96    (int (*)(...))__cxa_pure_virtual

Class Mapping::DoubleHash
   size=72 align=8
   base size=68 base align=8
Mapping::DoubleHash (0x0x7f155719b138) 0
    vptr=((& Mapping::DoubleHash::_ZTVN7Mapping10DoubleHashE) + 16u)
  Mapping::Gen (0x0x7f155754c480) 0
      primary-for Mapping::DoubleHash (0x0x7f155719b138)

Vtable for Mapping::DoubleHash15
Mapping::DoubleHash15::_ZTVN7Mapping12DoubleHash15E: 13u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    (int (*)(...))Mapping::DoubleHash15::~DoubleHash15
24    (int (*)(...))Mapping::DoubleHash15::~DoubleHash15
32    (int (*)(...))Mapping::DoubleHash::set
40    (int (*)(...))Mapping::DoubleHash::get
48    (int (*)(...))Mapping::DoubleHash::deletee
56    (int (*)(...))Mapping::DoubleHash::getFirst
64    (int (*)(...))Mapping::DoubleHash::getNext
72    (int (*)(...))Mapping::DoubleHash15::vi_scale
80    (int (*)(...))Mapping::DoubleHash15::vi_h1
88    (int (*)(...))Mapping::DoubleHash15::vi_h2
96    (int (*)(...))Mapping::DoubleHash15::vi_dtor

Class Mapping::DoubleHash15
   size=72 align=8
   base size=68 base align=8
Mapping::DoubleHash15 (0x0x7f155719b1a0) 0
    vptr=((& Mapping::DoubleHash15::_ZTVN7Mapping12DoubleHash15E) + 16u)
  Mapping::DoubleHash (0x0x7f155719b208) 0
      primary-for Mapping::DoubleHash15 (0x0x7f155719b1a0)
    Mapping::Gen (0x0x7f155754c5a0) 0
        primary-for Mapping::DoubleHash (0x0x7f155719b208)

Class Mapping
   size=1 align=1
   base size=0 base align=1
Mapping (0x0x7f155754c3c0) 0 empty

Class Error::Policy
   size=64 align=8
   base size=64 base align=8
Error::Policy (0x0x7f155754c660) 0

Class Error::Cleanup
   size=32 align=8
   base size=32 base align=8
Error::Cleanup (0x0x7f155754c6c0) 0

Class Error
   size=1 align=1
   base size=0 base align=1
Error (0x0x7f155754c600) 0 empty

Class __locale_struct
   size=232 align=8
   base size=232 base align=8
__locale_struct (0x0x7f155754c720) 0

Class <anonymous struct>
   size=8 align=4
   base size=8 base align=4
<anonymous struct> (0x0x7f155754c780) 0

Class wait::<anonymous struct>
   size=4 align=4
   base size=4 base align=4
wait::<anonymous struct> (0x0x7f155754c840) 0

Class wait::<anonymous struct>
   size=4 align=4
   base size=4 base align=4
wait::<anonymous struct> (0x0x7f155754c8a0) 0

Class wait
   size=4 align=4
   base size=4 base align=4
wait (0x0x7f155754c7e0) 0

Class <anonymous struct>
   size=8 align=4
   base size=8 base align=4
<anonymous struct> (0x0x7f155754c900) 0

Class <anonymous struct>
   size=16 align=8
   base size=16 base align=8
<anonymous struct> (0x0x7f155754c960) 0

Class <anonymous struct>
   size=16 align=8
   base size=16 base align=8
<anonymous struct> (0x0x7f155754c9c0) 0

Class <anonymous struct>
   size=128 align=8
   base size=128 base align=8
<anonymous struct> (0x0x7f155754ca20) 0

Class timespec
   size=16 align=8
   base size=16 base align=8
timespec (0x0x7f155754ca80) 0

Class timeval
   size=16 align=8
   base size=16 base align=8
timeval (0x0x7f155754cae0) 0

Class <anonymous struct>
   size=128 align=8
   base size=128 base align=8
<anonymous struct> (0x0x7f155754cb40) 0

Class pthread_attr_t
   size=56 align=8
   base size=56 base align=8
pthread_attr_t (0x0x7f155754cba0) 0

Class __pthread_internal_list
   size=16 align=8
   base size=16 base align=8
__pthread_internal_list (0x0x7f155754cc00) 0

Class <anonymous union>::__pthread_mutex_s
   size=40 align=8
   base size=40 base align=8
<anonymous union>::__pthread_mutex_s (0x0x7f155754ccc0) 0

Class <anonymous union>
   size=40 align=8
   base size=40 base align=8
<anonymous union> (0x0x7f155754cc60) 0

Class <anonymous union>
   size=4 align=4
   base size=4 base align=4
<anonymous union> (0x0x7f155754cd20) 0

Class <anonymous union>::<anonymous struct>
   size=48 align=8
   base size=48 base align=8
<anonymous union>::<anonymous struct> (0x0x7f155754cde0) 0

Class <anonymous union>
   size=48 align=8
   base size=48 base align=8
<anonymous union> (0x0x7f155754cd80) 0

Class <anonymous union>
   size=4 align=4
   base size=4 base align=4
<anonymous union> (0x0x7f155754ce40) 0

Class <anonymous union>::<anonymous struct>
   size=56 align=8
   base size=56 base align=8
<anonymous union>::<anonymous struct> (0x0x7f155754cf00) 0

Class <anonymous union>
   size=56 align=8
   base size=56 base align=8
<anonymous union> (0x0x7f155754cea0) 0

Class <anonymous union>
   size=8 align=8
   base size=8 base align=8
<anonymous union> (0x0x7f155754cf60) 0

Class <anonymous union>
   size=32 align=8
   base size=32 base align=8
<anonymous union> (0x0x7f15572d8000) 0

Class <anonymous union>
   size=4 align=4
   base size=4 base align=4
<anonymous union> (0x0x7f15572d8060) 0

Class random_data
   size=48 align=8
   base size=48 base align=8
random_data (0x0x7f15572d80c0) 0

Class drand48_data
   size=24 align=8
   base size=24 base align=8
drand48_data (0x0x7f15572d8120) 0

