Class GenBuffer::Sub
   size=32 align=8
   base size=32 base align=8
GenBuffer::Sub (0x0x7fcb8257f780) 0

Class GenBuffer::SubW
   size=32 align=8
   base size=32 base align=8
GenBuffer::SubW (0x0x7fcb8257f7e0) 0

Vtable for GenBuffer::Writable
GenBuffer::Writable::_ZTVN9GenBuffer8WritableE: 8u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    (int (*)(...))__cxa_pure_virtual
24    (int (*)(...))__cxa_pure_virtual
32    0u
40    0u
48    (int (*)(...))GenBuffer::Writable::vformat
56    (int (*)(...))GenBuffer::Writable::vformat

Class GenBuffer::Writable
   size=8 align=8
   base size=8 base align=8
GenBuffer::Writable (0x0x7fcb8257f840) 0 nearly-empty
    vptr=((& GenBuffer::Writable::_ZTVN9GenBuffer8WritableE) + 16u)

Vtable for GenBuffer::Readable
GenBuffer::Readable::_ZTVN9GenBuffer8ReadableE: 8u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    (int (*)(...))__cxa_pure_virtual
24    (int (*)(...))GenBuffer::Readable::vi_read
32    (int (*)(...))GenBuffer::Readable::vi_availh
40    (int (*)(...))GenBuffer::Readable::vi_rewind
48    0u
56    0u

Class GenBuffer::Readable
   size=8 align=8
   base size=8 base align=8
GenBuffer::Readable (0x0x7fcb8257f8a0) 0 nearly-empty
    vptr=((& GenBuffer::Readable::_ZTVN9GenBuffer8ReadableE) + 16u)

Vtable for GenBuffer
GenBuffer::_ZTV9GenBuffer: 13u entries
0     (int (*)(...))0
8     (int (*)(...))0
16    0u
24    0u
32    (int (*)(...))__cxa_pure_virtual
40    (int (*)(...))__cxa_pure_virtual
48    (int (*)(...))__cxa_pure_virtual
56    (int (*)(...))__cxa_pure_virtual
64    (int (*)(...))GenBuffer::operator void*
72    (int (*)(...))GenBuffer::operator!
80    (int (*)(...))GenBuffer::copyRange
88    (int (*)(...))GenBuffer::cmp
96    (int (*)(...))GenBuffer::cmp

Class GenBuffer
   size=8 align=8
   base size=8 base align=8
GenBuffer (0x0x7fcb8257f720) 0 nearly-empty
    vptr=((& GenBuffer::_ZTV9GenBuffer) + 16u)

Vtable for SimBuffer::Flat
SimBuffer::Flat::_ZTVN9SimBuffer4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   (int (*)(...))SimBuffer::Flat::~Flat
112   (int (*)(...))SimBuffer::Flat::~Flat
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::Flat
SimBuffer::Flat::_ZTTN9SimBuffer4FlatE: 2u entries
0     ((& SimBuffer::Flat::_ZTVN9SimBuffer4FlatE) + 104u)
8     ((& SimBuffer::Flat::_ZTVN9SimBuffer4FlatE) + 104u)

Class SimBuffer::Flat
   size=24 align=8
   base size=24 base align=8
SimBuffer::Flat (0x0x7fcb825aa138) 0
    vptridx=0u vptr=((& SimBuffer::Flat::_ZTVN9SimBuffer4FlatE) + 104u)
  GenBuffer (0x0x7fcb8257f960) 0 nearly-empty virtual
      primary-for SimBuffer::Flat (0x0x7fcb825aa138)
      vptridx=8u vbaseoffset=-104

Vtable for SimBuffer::Static
SimBuffer::Static::_ZTVN9SimBuffer6StaticE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   (int (*)(...))SimBuffer::Static::~Static
112   (int (*)(...))SimBuffer::Static::~Static
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

Construction vtable for SimBuffer::Flat (0x0x7fcb825aa208 instance) in SimBuffer::Static
SimBuffer::Static::_ZTCN9SimBuffer6StaticE0_NS_4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   0u
112   0u
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::Static
SimBuffer::Static::_ZTTN9SimBuffer6StaticE: 4u entries
0     ((& SimBuffer::Static::_ZTVN9SimBuffer6StaticE) + 104u)
8     ((& SimBuffer::Static::_ZTCN9SimBuffer6StaticE0_NS_4FlatE) + 104u)
16    ((& SimBuffer::Static::_ZTCN9SimBuffer6StaticE0_NS_4FlatE) + 104u)
24    ((& SimBuffer::Static::_ZTVN9SimBuffer6StaticE) + 104u)

Class SimBuffer::Static
   size=24 align=8
   base size=24 base align=8
SimBuffer::Static (0x0x7fcb825aa1a0) 0
    vptridx=0u vptr=((& SimBuffer::Static::_ZTVN9SimBuffer6StaticE) + 104u)
  SimBuffer::Flat (0x0x7fcb825aa208) 0
      primary-for SimBuffer::Static (0x0x7fcb825aa1a0)
      subvttidx=8u
    GenBuffer (0x0x7fcb8257f9c0) 0 nearly-empty virtual
        primary-for SimBuffer::Flat (0x0x7fcb825aa208)
        vptridx=24u vbaseoffset=-104

Vtable for SimBuffer::Fixed
SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   (int (*)(...))SimBuffer::Fixed::~Fixed
112   (int (*)(...))SimBuffer::Fixed::~Fixed
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

Construction vtable for SimBuffer::Flat (0x0x7fcb825aa2d8 instance) in SimBuffer::Fixed
SimBuffer::Fixed::_ZTCN9SimBuffer5FixedE0_NS_4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   0u
112   0u
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::Fixed
SimBuffer::Fixed::_ZTTN9SimBuffer5FixedE: 4u entries
0     ((& SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE) + 104u)
8     ((& SimBuffer::Fixed::_ZTCN9SimBuffer5FixedE0_NS_4FlatE) + 104u)
16    ((& SimBuffer::Fixed::_ZTCN9SimBuffer5FixedE0_NS_4FlatE) + 104u)
24    ((& SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE) + 104u)

Class SimBuffer::Fixed
   size=24 align=8
   base size=24 base align=8
SimBuffer::Fixed (0x0x7fcb825aa270) 0
    vptridx=0u vptr=((& SimBuffer::Fixed::_ZTVN9SimBuffer5FixedE) + 104u)
  SimBuffer::Flat (0x0x7fcb825aa2d8) 0
      primary-for SimBuffer::Fixed (0x0x7fcb825aa270)
      subvttidx=8u
    GenBuffer (0x0x7fcb8257fa20) 0 nearly-empty virtual
        primary-for SimBuffer::Flat (0x0x7fcb825aa2d8)
        vptridx=24u vbaseoffset=-104

Vtable for SimBuffer::Appendable
SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE: 34u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551608u
168   (int (*)(...))-8
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

VTT for SimBuffer::Appendable
SimBuffer::Appendable::_ZTTN9SimBuffer10AppendableE: 2u entries
0     ((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 24u)
8     ((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 184u)

Class SimBuffer::Appendable
   size=16 align=8
   base size=8 base align=8
SimBuffer::Appendable (0x0x7fcb8263f000) 0 nearly-empty
    vptridx=0u vptr=((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 24u)
  GenBuffer (0x0x7fcb8257fa80) 8 nearly-empty virtual
      vptridx=8u vbaseoffset=-24 vptr=((& SimBuffer::Appendable::_ZTVN9SimBuffer10AppendableE) + 184u)
  GenBuffer::Writable (0x0x7fcb8257fae0) 0 nearly-empty
      primary-for SimBuffer::Appendable (0x0x7fcb8263f000)

Class SimBuffer::Linked::Node
   size=24 align=8
   base size=24 base align=8
SimBuffer::Linked::Node (0x0x7fcb8257fc00) 0

Vtable for SimBuffer::Linked
SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE: 38u entries
0     24u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    (int (*)(...))SimBuffer::Linked::~Linked
48    (int (*)(...))SimBuffer::Linked::~Linked
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))SimBuffer::Linked::vi_mkend
80    (int (*)(...))SimBuffer::Linked::vi_mkbeg
88    (int (*)(...))SimBuffer::Linked::getLength
96    (int (*)(...))SimBuffer::Linked::each_sub
104   (int (*)(...))SimBuffer::Linked::first_sub
112   (int (*)(...))SimBuffer::Linked::next_sub
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551592u
168   18446744073709551592u
176   18446744073709551592u
184   18446744073709551592u
192   18446744073709551592u
200   (int (*)(...))-24
208   (int (*)(...))0
216   (int (*)(...))SimBuffer::Linked::_ZTv0_n24_N9SimBuffer6LinkedD1Ev
224   (int (*)(...))SimBuffer::Linked::_ZTv0_n24_N9SimBuffer6LinkedD0Ev
232   (int (*)(...))SimBuffer::Linked::_ZTv0_n32_NK9SimBuffer6Linked9getLengthEv
240   (int (*)(...))SimBuffer::Linked::_ZTv0_n40_NK9SimBuffer6Linked8each_subEPFvPKcmPvES3_
248   (int (*)(...))SimBuffer::Linked::_ZTv0_n48_NK9SimBuffer6Linked9first_subERN9GenBuffer3SubE
256   (int (*)(...))SimBuffer::Linked::_ZTv0_n56_NK9SimBuffer6Linked8next_subERN9GenBuffer3SubE
264   (int (*)(...))GenBuffer::operator void*
272   (int (*)(...))GenBuffer::operator!
280   (int (*)(...))GenBuffer::copyRange
288   (int (*)(...))GenBuffer::cmp
296   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Appendable (0x0x7fcb8263f150 instance) in SimBuffer::Linked
SimBuffer::Linked::_ZTCN9SimBuffer6LinkedE0_NS_10AppendableE: 34u entries
0     24u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551592u
168   (int (*)(...))-24
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

VTT for SimBuffer::Linked
SimBuffer::Linked::_ZTTN9SimBuffer6LinkedE: 4u entries
0     ((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 24u)
8     ((& SimBuffer::Linked::_ZTCN9SimBuffer6LinkedE0_NS_10AppendableE) + 24u)
16    ((& SimBuffer::Linked::_ZTCN9SimBuffer6LinkedE0_NS_10AppendableE) + 184u)
24    ((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 216u)

Class SimBuffer::Linked
   size=32 align=8
   base size=24 base align=8
SimBuffer::Linked (0x0x7fcb825aa3a8) 0
    vptridx=0u vptr=((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 24u)
  SimBuffer::Appendable (0x0x7fcb8263f150) 0 nearly-empty
      primary-for SimBuffer::Linked (0x0x7fcb825aa3a8)
      subvttidx=8u
    GenBuffer (0x0x7fcb8257fb40) 24 nearly-empty virtual
        vptridx=24u vbaseoffset=-24 vptr=((& SimBuffer::Linked::_ZTVN9SimBuffer6LinkedE) + 216u)
    GenBuffer::Writable (0x0x7fcb8257fba0) 0 nearly-empty
        primary-for SimBuffer::Appendable (0x0x7fcb8263f150)

Vtable for SimBuffer::Resizable
SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE: 35u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))SimBuffer::Resizable::vi_mkend
80    (int (*)(...))SimBuffer::Resizable::vi_mkbeg
88    (int (*)(...))__cxa_pure_virtual
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   0u
168   18446744073709551608u
176   (int (*)(...))-8
184   (int (*)(...))0
192   0u
200   0u
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))__cxa_pure_virtual
240   (int (*)(...))GenBuffer::operator void*
248   (int (*)(...))GenBuffer::operator!
256   (int (*)(...))GenBuffer::copyRange
264   (int (*)(...))GenBuffer::cmp
272   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Appendable (0x0x7fcb8263f4d0 instance) in SimBuffer::Resizable
SimBuffer::Resizable::_ZTCN9SimBuffer9ResizableE0_NS_10AppendableE: 34u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551608u
168   (int (*)(...))-8
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

VTT for SimBuffer::Resizable
SimBuffer::Resizable::_ZTTN9SimBuffer9ResizableE: 4u entries
0     ((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 24u)
8     ((& SimBuffer::Resizable::_ZTCN9SimBuffer9ResizableE0_NS_10AppendableE) + 24u)
16    ((& SimBuffer::Resizable::_ZTCN9SimBuffer9ResizableE0_NS_10AppendableE) + 184u)
24    ((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 192u)

Class SimBuffer::Resizable
   size=16 align=8
   base size=8 base align=8
SimBuffer::Resizable (0x0x7fcb825aa4e0) 0 nearly-empty
    vptridx=0u vptr=((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 24u)
  SimBuffer::Appendable (0x0x7fcb8263f4d0) 0 nearly-empty
      primary-for SimBuffer::Resizable (0x0x7fcb825aa4e0)
      subvttidx=8u
    GenBuffer (0x0x7fcb8257fd20) 8 nearly-empty virtual
        vptridx=24u vbaseoffset=-24 vptr=((& SimBuffer::Resizable::_ZTVN9SimBuffer9ResizableE) + 192u)
    GenBuffer::Writable (0x0x7fcb8257fd80) 0 nearly-empty
        primary-for SimBuffer::Appendable (0x0x7fcb8263f4d0)

Vtable for SimBuffer::B
SimBuffer::B::_ZTVN9SimBuffer1BE: 40u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::B::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    (int (*)(...))SimBuffer::B::~B
48    (int (*)(...))SimBuffer::B::~B
56    (int (*)(...))SimBuffer::B::vformat
64    (int (*)(...))SimBuffer::B::vformat
72    (int (*)(...))SimBuffer::Resizable::vi_mkend
80    (int (*)(...))SimBuffer::Resizable::vi_mkbeg
88    (int (*)(...))SimBuffer::B::vi_grow2
96    (int (*)(...))SimBuffer::B::operator void*
104   (int (*)(...))SimBuffer::B::operator!
112   0u
120   0u
128   0u
136   0u
144   18446744073709551608u
152   18446744073709551608u
160   0u
168   0u
176   0u
184   0u
192   18446744073709551608u
200   (int (*)(...))-8
208   (int (*)(...))0
216   (int (*)(...))SimBuffer::B::_ZThn8_N9SimBuffer1BD1Ev
224   (int (*)(...))SimBuffer::B::_ZThn8_N9SimBuffer1BD0Ev
232   (int (*)(...))SimBuffer::Flat::getLength
240   (int (*)(...))SimBuffer::Flat::each_sub
248   (int (*)(...))SimBuffer::Flat::first_sub
256   (int (*)(...))SimBuffer::Flat::next_sub
264   (int (*)(...))SimBuffer::B::_ZThn8_NK9SimBuffer1BcvPvEv
272   (int (*)(...))SimBuffer::B::_ZThn8_NK9SimBuffer1BntEv
280   (int (*)(...))SimBuffer::Flat::copyRange
288   (int (*)(...))GenBuffer::cmp
296   (int (*)(...))SimBuffer::Flat::cmp
304   (int (*)(...))SimBuffer::Flat::cmp
312   (int (*)(...))SimBuffer::Flat::getAt0

Construction vtable for SimBuffer::Resizable (0x0x7fcb825aa618 instance) in SimBuffer::B
SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_9ResizableE: 35u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))SimBuffer::Resizable::vi_mkend
80    (int (*)(...))SimBuffer::Resizable::vi_mkbeg
88    (int (*)(...))__cxa_pure_virtual
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   0u
168   18446744073709551608u
176   (int (*)(...))-8
184   (int (*)(...))0
192   0u
200   0u
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))__cxa_pure_virtual
240   (int (*)(...))GenBuffer::operator void*
248   (int (*)(...))GenBuffer::operator!
256   (int (*)(...))GenBuffer::copyRange
264   (int (*)(...))GenBuffer::cmp
272   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Appendable (0x0x7fcb8263f690 instance) in SimBuffer::B
SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_10AppendableE: 34u entries
0     8u
8     (int (*)(...))0
16    (int (*)(...))0
24    (int (*)(...))SimBuffer::Appendable::vi_write
32    (int (*)(...))SimBuffer::Appendable::vi_putcc
40    0u
48    0u
56    (int (*)(...))GenBuffer::Writable::vformat
64    (int (*)(...))GenBuffer::Writable::vformat
72    (int (*)(...))__cxa_pure_virtual
80    (int (*)(...))__cxa_pure_virtual
88    0u
96    0u
104   0u
112   0u
120   0u
128   0u
136   0u
144   0u
152   0u
160   18446744073709551608u
168   (int (*)(...))-8
176   (int (*)(...))0
184   0u
192   0u
200   (int (*)(...))__cxa_pure_virtual
208   (int (*)(...))__cxa_pure_virtual
216   (int (*)(...))__cxa_pure_virtual
224   (int (*)(...))__cxa_pure_virtual
232   (int (*)(...))GenBuffer::operator void*
240   (int (*)(...))GenBuffer::operator!
248   (int (*)(...))GenBuffer::copyRange
256   (int (*)(...))GenBuffer::cmp
264   (int (*)(...))GenBuffer::cmp

Construction vtable for SimBuffer::Flat (0x0x7fcb825aa680 instance) in SimBuffer::B
SimBuffer::B::_ZTCN9SimBuffer1BE8_NS_4FlatE: 26u entries
0     0u
8     0u
16    0u
24    0u
32    0u
40    0u
48    0u
56    0u
64    0u
72    0u
80    0u
88    (int (*)(...))0
96    (int (*)(...))0
104   0u
112   0u
120   (int (*)(...))SimBuffer::Flat::getLength
128   (int (*)(...))SimBuffer::Flat::each_sub
136   (int (*)(...))SimBuffer::Flat::first_sub
144   (int (*)(...))SimBuffer::Flat::next_sub
152   (int (*)(...))SimBuffer::Flat::operator void*
160   (int (*)(...))SimBuffer::Flat::operator!
168   (int (*)(...))SimBuffer::Flat::copyRange
176   (int (*)(...))GenBuffer::cmp
184   (int (*)(...))SimBuffer::Flat::cmp
192   (int (*)(...))SimBuffer::Flat::cmp
200   (int (*)(...))SimBuffer::Flat::getAt0

VTT for SimBuffer::B
SimBuffer::B::_ZTTN9SimBuffer1BE: 9u entries
0     ((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 24u)
8     ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_9ResizableE) + 24u)
16    ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_10AppendableE) + 24u)
24    ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_10AppendableE) + 184u)
32    ((& SimBuffer::B::_ZTCN9SimBuffer1BE0_NS_9ResizableE) + 192u)
40    ((& SimBuffer::B::_ZTCN9SimBuffer1BE8_NS_4FlatE) + 104u)
48    ((& SimBuffer::B::_ZTCN9SimBuffer1BE8_NS_4FlatE) + 104u)
56    ((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 216u)
64    ((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 216u)

Class SimBuffer::B
   size=48 align=8
   base size=48 base align=8
SimBuffer::B (0x0x7fcb8263f620) 0
    vptridx=0u vptr=((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 24u)
  SimBuffer::Resizable (0x0x7fcb825aa618) 0 nearly-empty
      primary-for SimBuffer::B (0x0x7fcb8263f620)
      subvttidx=8u
    SimBuffer::Appendable (0x0x7fcb8263f690) 0 nearly-empty
        primary-for SimBuffer::Resizable (0x0x7fcb825aa618)
        subvttidx=16u
      GenBuffer (0x0x7fcb8257fde0) 8 nearly-empty virtual
          primary-for SimBuffer::Flat (0x0x7fcb825aa680)
          vptridx=56u vbaseoffset=-24
      GenBuffer::Writable (0x0x7fcb8257fe40) 0 nearly-empty
          primary-for SimBuffer::Appendable (0x0x7fcb8263f690)
  SimBuffer::Flat (0x0x7fcb825aa680) 8
      subvttidx=40u vptridx=64u vptr=((& SimBuffer::B::_ZTVN9SimBuffer1BE) + 216u)
    GenBuffer (0x0x7fcb8257fde0) alternative-path

Class SimBuffer
   size=1 align=1
   base size=0 base align=1
SimBuffer (0x0x7fcb8257f900) 0 empty

Class __locale_struct
   size=232 align=8
   base size=232 base align=8
__locale_struct (0x0x7fcb8257fea0) 0

Class copydata_t
   size=32 align=8
   base size=32 base align=8
copydata_t (0x0x7fcb8257ff00) 0

