# tragesym test1:
# this is a source file for tragesym
# please take a look at the docs and the template.src file for more informations

[options]
wordswap=yes
rotate_labels=no
sort_labels=yes
generate_pinseq=no
sym_width=2600
pinwidthvertical=400
pinwidthhorizontal=600

[geda_attr]
version=20060113 1
name=TEST1
device=devTEST1
refdes=U?
footprint=SO20
description=pin sorting test, pin sequence test
documentation=http://url_to_the_datasheet.com/datasheet.pdf
author=Werner Hoch <werner.ho(AT)gmx.de>
numslots=4
use-license
dist-license=
special-attribute=unknown
slot=1
slotdef=1:1,2,3
slotdef=2:4,5,6
slotdef=3:7,8,9
slotdef=4:10,11,12
comment=bla
comment=blub
comment=blablub

[pins]
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	
#-----------------------------------------------------
1	21	i	line	l		hello
2	20	o	clk	l		\_neg\_
3	19	out	dot	l		\_n\_0\_n\_
4		pwr	none		GND
5	18	IO	line	l		\_ABC\_ (DEF)
6	17	out	clk	l		xx\_XX\_xx
7	16	out	dot	l		\_Reset\_
8		pwr	none		AGND
9	15	I/O	line	l		A12a100xx
10	14	out	clk	l		A12a100
11	13	out	dot	l		ner
12		pwr	none		AVcc
13	12	i/o	line	l		A1
14	11	out	clk	l		A12
15	10	out	dot	l		A2
16		pwr	none		Vcc
17	9	in	dotclk	l		first
18	8	in	dotclk	r		n\_exe\_n
19	7	in	dotclk	t		this
20 	6	in	dotclk	b		other
21	5	in	dot	b		\_Reset\_
22	4	out	line	t		PD1 (\_SS\_)
23	3	pas	clk	r		PD2 (\_xxx\_hello\_sss\_)
24	2	p	dot	r		PD3 (x_no_over)
25	1	io	clk	r		PD4 (\\\_strange\\\_)

