DREAL is the hierarchical real layout editor of Alliance.
It is based on the same sources than GRAAL.
There are no integrated design rule checker and extractor.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
ENTITY ram IS
port ( A : in std_logic_vector(5 downto 0);
CEB, WEB : in std_logic;
INN : in std_logic_vector(7 downto 0);
OUTT : out std_logic_vector(7 downto 0)
);
END ram;
ARCHITECTURE dataflow_view OF ram IS
SUBTYPE TYPE_WORD IS std_logic_vector(7 downto 0);
TYPE TYPE_RAM IS ARRAY(63 DOWNTO 0) OF TYPE_WORD;
SIGNAL memory : TYPE_RAM;
BEGIN
OUTT <= memory( CONV_INTEGER( A ) );
RAM_0 : PROCESS( CEB )
BEGIN
IF (CEB='1' AND CEB'EVENT )
THEN IF (WEB='0')
THEN memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;
END dataflow_view;
ENTITY circuit is
PORT
( ck : in BIT;
jour : in BIT;
reset : in BIT;
vdd : in BIT;
vss : in BIT;
i : in BIT_VECTOR(3 DOWNTO 0);
porte : out BIT;
alarm : out BIT
);
END circuit;
ARCHITECTURE MOORE OF circuit is
TYPE ETAT_TYPE IS (E0, E1, E2, E3, E4, E5, EA);
SIGNAL EF, CS : ETAT_TYPE;
CONSTANT digit0 : BIT_VECTOR (3 DOWNTO 0) := B"1111" ; -- O
....
--PRAGMA CURRENT_STATE CS
--PRAGMA NEXT_STATE EF
--PRAGMA CLOCK ck
--PRAGMA FIRST_STATE E0
BEGIN
PROCESS ( CS, i)
BEGIN
IF ( reset = '1' )
THEN
EF <= E0; porte <= '0'; alarm <= '0'; ELSE
CASE CS is
WHEN E0 =>
porte <= '0'; alarm <= '0';
IF ( i = digit0 ) THEN
IF ( jour = '1' ) THEN EF <= E5;
ELSE EF <= EA;
END IF;
ELSE
IF ( i = digit1 ) THEN EF <= E1;
ELSE IF ( jour = '1' ) THEN EF <= E0;
ELSE EF <= EA;
END IF;
END IF;
END IF;
WHEN E1 =>
....
END CASE;
END IF;
END PROCESS;
PROCESS( ck )
BEGIN
IF ( ck = '1' AND NOT ck'STABLE ) THEN CS <= EF;
END IF;
END PROCESS;
END MOORE;
ENTITY addaccu IS
PORT(
clr : IN BIT;
ld : IN BIT;
outs : IN BIT_VECTOR(15 DOWNTO 0);
clk : IN BIT;
result : OUT BIT_VECTOR(15 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT
);
END addaccu;
ARCHITECTURE VBE OF addaccu IS
SIGNAL rtlsum_0 : BIT_VECTOR(15 DOWNTO 0);
SIGNAL rtlcarry_0 : BIT_VECTOR(15 DOWNTO 0);
SIGNAL resultint : REG_VECTOR(15 DOWNTO 0) REGISTER;
BEGIN
rtlcarry_0(0) < '0';
rtlsum_0 < ((resultint XOR outs) XOR rtlcarry_0);
rtlcarry_0(15 downto 1) < (((resultint(14 downto 0) AND outs(14 downto 0)) OR
(resultint(14 downto 0) AND rtlcarry_0(14 downto 0))) OR
(outs(14 downto 0) AND rtlcarry_0(14 downto 0)));
result < resultint;
LABEL1 : BLOCK ((clk = '1') AND NOT(clk'STABLE) )
BEGIN
resultint < GUARDED "0000000000000000" WHEN clr ELSE
rtlsum_0 WHEN (NOT(clr) AND ld) ELSE resultint;
END BLOCK LABEL1;
END VBE;
ENTITY digi IS
PORT (
ck : in BIT ;
jour : in BIT ;
reset : in BIT ;
vdd : in BIT ;
vss : in BIT ;
i : in BIT_VECTOR(3 DOWNTO 0) ;
porte : out BIT ;
alarm : out BIT
);
END digi;
ARCHITECTURE VST OF digi IS
COMPONENT nxr2_x1
port (
i0 : in BIT ;
i1 : in BIT ;
nq : out BIT ;
vdd : in BIT ;
vss : in BIT
);
END COMPONENT;
....
SIGNAL mbk_buf_not_aux1 : BIT;
....
BEGIN
not_aux12_ins : nxr2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => not_aux12,
i1 => i(3),
i0 => i(1));
....
end VST;
in clk B;;
in rst B;;
in stb B;;
in a (7 downto 0) X;;
in b (7 downto 0) X;;
out result (15 downto 0) X;;
out done B;
begin
....
: 1 0 0 00 00 ?0006 ?0;
: 0 0 0 00 00 ?0006 ?0;
: 1 0 0 00 00 ?0006 ?1;
: 0 0 0 00 00 ?0006 ?1;
: 1 0 0 00 00 ?0006 ?1;
: 0 0 0 00 00 ?0006 ?1;
end;
V ALLIANCE : 6
H digi,P, 1/10/2002,100
A 0,0,28000,30000
C 28000,29700,600,vdd,7,EAST,ALU1
C 21000,0,200,alarm,0,SOUTH,ALU2
C 2000,30000,200,ck,0,NORTH,ALU2
....
S 0,25000,28000,25000,1200,vss,RIGHT,ALU1
S 0,20000,28000,20000,1200,vdd,RIGHT,ALU1
S 0,10000,28000,10000,1200,vdd,RIGHT,ALU1
....
I 24000,0,a3_x2,a3_x2_4_ins,SYM_Y
I 4000,0,na2_x1,na2_x1_2_ins,SYM_Y
....
V 2000,29500,CONT_VIA2,*
V 2000,30000,CONT_VIA2,*
V 2500,14000,CONT_VIA2,*
V 2500,19000,CONT_VIA2,*
...
EOF
V ALLIANCE : 6
H digi_e,L,01/10/2002
C alarm,UNKNOWN,EXTERNAL,12
C ck,UNKNOWN,EXTERNAL,40
...
C vdd,UNKNOWN,EXTERNAL,1
C vss,UNKNOWN,EXTERNAL,21
I na2_x1,na2_x1_2_ins
C i0,UNKNOWN,INTERNAL,4
C i1,UNKNOWN,INTERNAL,6
...
S 4,INTERNAL,not_aux14
S 3,INTERNAL,circuit_cs_0
S 2,INTERNAL,circuit_cs_2
S 1,EXTERNAL,vdd
EOF